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Hardware Description Languages for FPGA Design

This course is part of FPGA Design for Embedded Systems Specialization

Instructors: Timothy Scherr +1 more

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What you'll learn

Explain the role of HDLs in design entry and verification for FPGAs and ASICs

Utilize HDL software tools for FPGA development

Skills you'll gain

Computer Engineering

System Design and Implementation

Development Testing

Programming Principles

Debugging

Functional Testing

Simulations

Hardware Architecture

Verification And Validation

There are 4 modules in this course

Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

VHDL Logic Design Techniques

Basics of Verilog

Verilog and System Verilog Design Techniques